Yamaha YMF724F Manuel d'utilisateur

YMF724FDS-1YAMAHACORPORATIONSeptember 21, 1998PreliminaryOVERVIEWYMF724F (DS-1) is a high performance audio controller for the PCI Bus. DS-1 consists

YMF724F September 21, 1998-10-1-2. PCI Configuration RegisterIn addition to the Configuration Register defined by PCI Revision

YMF724F September 21, 1998-11-00 - 01h: Vendor IDRead OnlyDefault: 1073hAccess Bus Width: 8, 16, 32-bitb15 b14 b13 b12 b11 b10

YMF724F September 21, 1998-12-b8...SER: SERR# EnableThis bit enables DS-1 to drive SERR#. “0”: Do not drive SERR

YMF724F September 21, 1998-13-08h: Revision IDRead OnlyDefault: 03hAccess Bus Width: 8, 16, 32-bitb7 b6 b5 b4 b3 b2 b1 b0Revis

YMF724F September 21, 1998-14-0Dh: Latency TimerRead / WriteDefault: 00hAccess Bus Width: 8, 16, 32-bitb7 b6 b5 b4 b3 b2 b1 b0

YMF724F September 21, 1998-15-2C-2Dh: Subsystem Vendor IDRead OnlyDefault: 1073hAccess Bus Width: 8, 16, 32-bitb15 b14 b13 b12

YMF724F September 21, 1998-16-3Ch: Interrupt LineRead / WriteDefault: 00hAccess Bus Width: 8, 16, 32-bitb7 b6 b5 b4 b3 b2 b1 b

YMF724F September 21, 1998-17-40 - 41h: Legacy Audio ControlRead / WriteDefault: 907FhAccess Bus Width: 8, 16, 32-bitb15 b14 b

YMF724F September 21, 1998-18-b[7:6] ...SDMA: Sound Blaster DMA-8 Channel SelectThese bits select the DMA channel for t

YMF724F September 21, 1998-19-42 - 43h: Extended Legacy Audio ControlRead / WriteDefault: 0000hAccess Bus Width: 8, 16, 32-bit

YMF724F September 21, 1998-2-LOGOS1. GM system level 1GM system level 1 is a world standard format about MIDI synthesizer whic

YMF724F September 21, 1998-20-b[12:11] ...SMOD: SB DMA modeThese bits determine the protocol to achieve the DMAC(8237) func

YMF724F September 21, 1998-21-46-47h: Subsystem ID Write RegisterRead / WriteDefault: 000DhAccess Bus Width: 16-bitb15 b14 b13

YMF724F September 21, 1998-22-b2...DPLL1: Disable PLL1 Clock OscillationSetting this bit to “1” disables the osci

YMF724F September 21, 1998-23-b12...PR4: AC-2 Power down Control 4This bit controls the power state of the AC-link

YMF724F September 21, 1998-24-4C-4Dh: D-DMA Slave ConfigurationRead / WriteDefault: 0000hAccess Bus Width: 8, 16, 32-bitb15 b1

YMF724F September 21, 1998-25-51h: Next Item PointerRead OnlyDefault: 00hAccess Bus Width: 8, 16, 32-bitb7 b6 b5 b4 b3 b2 b1 b

YMF724F September 21, 1998-26-54-55h: Power Management Control / StatusRead / WriteDefault: 0000hAccess Bus Width: 8, 16, 32-b

YMF724F September 21, 1998-27-2. ISA Compatible DeviceDS-1 contains the following functions to maintain the compatibility with

YMF724F September 21, 1998-28-DS-1 supports PC/PCI and D-DMA protocols to emulate the DMA of SB Pro on the PCI. In addition

YMF724F September 21, 1998-29-2-1. OPL3 BlockOPL3 Block is register compatible with YMF289B. However, Power Management regist

YMF724F September 21, 1998-3-PIN CONFIGURATIONYMF724F-VGP4GP5GP6GP7RXDTXDROMDO/VOLDW#ROMSK/VOLUP#VDD5VDD3VSSVSSIRQ5IRQ7IRQ9IRQ

YMF724F September 21, 1998-30-2-1-2. OPL3 Data RegisterOPL3 Data Register Array 0 (R/W):AddressD7D6D5D4D3D2D1D000 - 01h LSI TE

YMF724F September 21, 1998-31-2-2. Sound Blaster Pro BlockThis block emulates the DSP commands of Sound Blaster and Sound Blas

YMF724F September 21, 1998-32-2-2-1. DSP CommandThe following shows the list of DSP Commands that are supported by the SB Pro

YMF724F September 21, 1998-33-2-2-2. Sound Blaster Pro MixerThe following shows the register map of the Mixer section of Sound

YMF724F September 21, 1998-34-(1) Volume for MIDIMIDI Vol. (26h)01234567mute mute mute mute mute mute mute mute00000h 0000h 00

YMF724F September 21, 1998-35-2-2-3. SB Suspend / ResumeThe SB block can read the internal state as to support Suspend and Res

YMF724F September 21, 1998-36-F1h: Scan In/ Out DataRead / WriteDefault: 00hb7 b6 b5 b4 b3 b2 b1 b0SCAN DATAb[7:0] ...S

YMF724F September 21, 1998-37-2-3. MPU401This block is for transmitting and receiving MIDI data. It is compatible with UART

YMF724F September 21, 1998-38-3. DMA Emulation ProtocolThe former synthesizer LSI for the ISA bus such as the Sound Blaster us

YMF724F September 21, 1998-39-3-2. D-DMADS-1 provides the following registers to support D-DMA. D-DMA Slave Configuration R

YMF724F September 21, 1998-4-PIN DESCRIPTION1. PCI Bus Interface (53-pin)name I/O Type Size functionPCICLK I P PCI ClockRST# I

YMF724F September 21, 1998-40-4. Interrupt RoutingDS-1 supports three types of interrupts, interrupt signal on the PCI bus (IN

YMF724F September 21, 1998-41-6. Hardware Volume ControlThe hardware volume control determines the AC-2 master volume without

YMF724F September 21, 1998-42-ELECTRICAL CHARACTERISTICS1. Absolute Maximum RatingsItem Symbol Min. Max. Unit Power Supply Vo

YMF724F September 21, 1998-43-3. DC Characteristics Item Symbol Condition Min. Typ. Max. Unit High Level Input Voltage 1 VIH

YMF724F September 21, 1998-44-4. AC Characteristics 4-1. Master Clock (Fig.1)Item Symbol Min. Typ. Max. UnitXI24 Cycle Time

YMF724F September 21, 1998-45-4-3. PCI Interface (Fig.3, 4)Item Symbol Condition Min. Typ. Max. UnitPCICLK Cycle Time tPCYC3

YMF724F September 21, 1998-46-4-4. AC-2 / AC3F2 Master Clock (Fig.5)Item Symbol Min. Typ. Max. UnitCMCLK Cycle Time tCMCYC-

YMF724F September 21, 1998-47-CBCLKCSYNCCSDICSDO0.8 V1.5 V2.0 V0.8 V2.0 V0.8 V2.0 V0.8 V1.5 V2.0 VtCBIHIGHtCVALtCBILOWtCBICYCt

YMF724F September 21, 1998-48-ASCLKACDIACS, ACDO2.0 V0.8 V2.0 V0.8 V0.8 V1.5 V2.0 VtASCHIGHtASCLOWtASCCYCtACVALtACOHtACISUtACI

YMF724F September 21, 1998-49-EXTERNAL DIMENSIONSYMF724F-V(1.00)0-10˚0.50±0.20LEAD THICKNESS : 0.15+0.10 -0.06 20.00±0.3022.00

YMF724F September 21, 1998-5-3. YMF727(AC3F2) Interface (9-pin)name I/O type size functionXRST# O C 2mA Reset for local device

YMF724F September 21, 1998-50-IMPORTANT NOTICE1. Yamaha reserves the right to make changes to its Products and to this documen

YMF724F September 21, 1998-6-6. Miscellaneous (15-pin)name I/O type Size functionROMCS O T 3mA Chip select for external EEPROM

YMF724F September 21, 1998-7-BLOCK DIAGRAMPCI Bus InterfaceBUS MasterDMA Controller MemoryXG SynthesizerDirect Sound Acc. Wav

YMF724F September 21, 1998-8-SYSTEM DIAGRAMWaveInDeviceWaveOutDeviceMidiOutDeviceXG/DLSEngineDS-1 Slot Manager (Up to 64-sound

YMF724F September 21, 1998-9-FUNCTION OVERVIEW1. PCI INTERFACEDS-1 supports the PCI bus interface and complies to PCI revision